library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity PG is
port (	A:	in   std_logic;
		B:	in   std_logic;
		P:	out std_logic;
		G:	out std_logic
);
end PG;

architecture Structural of PG is
begin

	P <= A xor B;
	G <= A and B;

end Structural;

